Technical Field
The invention relates to an electronic apparatus. Particularly, the invention relates to a data processing method and an apparatus.
Related Art
In recent years, as customers have increasing demand on quality of multimedia data, transmission interface of the multimedia data is quickly developed. When the multimedia data is transmitted through a high resolution interface, a high-bandwidth digital content protection (HDCP) is usually used to prevent data from being stolen. When a user wants to watch the data protected by the HDCP, the user has to use a playing device and a display device inbuilt with a HDCP key. The playing device and the display device have to perform an authentication process for exchanging keys in order to successfully play the data. If a problem is occurred during the authentication process, the data protected by the HDCP may have problems of low resolution, poor sound quality or unable to be played when the data is played. A HDCP key set is generally composed of 40 keys of 56 bits. A production machine or a test machine can write the keys into a memory of a circuit to be tested (for example, the playing device and/or the display device) through a manner of one bit after another.
The test machine may write data (for example, the HDCP key or other data) into the memory of the circuit to be tested through a plurality of pins, so as to perform function test on the circuit to be tested. For example, FIG. 1 is a schematic diagram of an example of conventional signal timing between the test machine and the circuit to be tested. In order to perform a function test, a data pin used for transmitting data DATA1 and other control pins (for example, a clock pin used for transmitting a clock signal CLK1) are configured between the test machine and the circuit to be tested. The circuit to be tested receives the clock signal CLK1 through the clock pin, and receives the data DATA1 through the data pin. The circuit to be tested can sample/latch a bit value of the data DATA1 according to a timing of the clock signal CLK1, so as to generate corresponding data DATA2 in internal of the circuit to be tested. Besides the clock signal CLK1 and the data DATA1, the test machine further provides a plurality of programming signals of different functions to the memory in internal of the circuit to be tested. Through control of the programming signals output by the test machine, the circuit to be tested can write the data DATA2 into the memory in internal of the circuit to be tested. Therefore, besides the pin used for transmitting the clock signal CLK1 and the pin used for transmitting the data DATA1, a plurality of control pins are configured between the test machine and the circuit to be tested for transmitting the programming signals to the memory in internal of the circuit to be tested.
On the other hand, the memory of the circuit to be tested (for example, the playing device and/or the display device) can be a memory device/circuit of any type, for example, a one-time programmable (OTP) memory or other non-volatile memory. The bit writing operation (to write the keys into the OTP memory) generally consumes a plenty of time. When the data DATA2 is written into the OTP memory, the test machine generally writes the data DATA2 into the OTP memory in a way of one bit each time. When a data amount of the data DATA2 to be written into the OTP memory is huge, for example, when a HDCP key set composed of 40 keys of 56 bits is to be written into the OTP memory, or when a plurality of HDCP key sets are to be written into the OTP memory, the test machine has to consume a plenty of time to write the data DATA2 with the huge data amount into the OTP memory. In the embodiment of FIG. 1, a time length of each period of the clock signal CLK1 is T1. In order to ensure that each bit has enough time to complete the bit writing operation, the time length T1 of each period of the clock signal CLK1 has to be greater than a rated time length of the bit writing operation.